1. Field of the Invention
This invention relates generally to analog-to-digital converters. More particularly, it relates to high speed analog-to-digital converters using lookahead pipelined architecture and open-loop residue amplifiers.
2. Description of the Related Art
There is a need for high speed analog-to-digital converters (ADCs). For example, there is strong commercial interest in 10 Gbit/s serial data transmission. In order to enable high performance sampling detectors, such as the Viterbi detector, a higher receive SNR is required than is required for suboptimal detectors such as decision feedback equalization. In order to provide these higher SNRs, 10 Giga samples per second (GS/s) ADCs with 5-8 bits of accuracy are currently required.
However, power dissipation is a significant problem for higher speed ADCs. In fact, all previously reported multi-GHz ADCs use too much power to be considered viable for 10 Gbit/s serial data transmission applications. A useful figure of merit in evaluating the power efficiency of an ADC is the quantization energy EQ, expressed in picojoules per conversion step:
                              E          Q                =                  Power                                    2              ENOB                        ⁢                          (                              2                ⁢                                  F                  BW                                            )                                                          (        1        )            where Power is the power consumption in watts, ENOB is the effective number of bits of the ADC, and FBW is the full-speed bandwidth of the converter (equal to Fs/2 in a full Nyquist ADC). The presently reported state of the art for very high speed ADCs is 1.6 GS/s conversion rate but with quantization energy of 7.4 pJ/conv-step. A more power efficient ADC is reported at only 1.0 pJ/conv-step but it only has a conversion rate of 80 MS/s.
A goal of current ADCs is a conversion rate of 10 GS/s with a resolution of 5 bits per sample and a quantization energy of 0.3 pJ/conv-step. This goal is important in order to reduce overall system power to a point where 10 Gbit/s data transmission using the Viterbi detector would be commercially viable using current technology.
Two common architectures for high speed ADCs are flash and pipeline. The flash ADC is the simplest and inherently fastest ADC. It uses 2N-1 parallel comparators, where N is the number of bits. The incoming analog value is simultaneously applied to each of the comparators, with the aggregate results from all of the comparisons determining the digital representation. Besides complexity and power consumption that grows geometrically with resolution, high-resolution flash converters have tight offset requirements that further increase power consumption.
The pipelined ADC uses simpler, lower resolution ADC stages which work concurrently on different samples of the input, so the throughput is equal to the speed of a given stage and is almost independent of the number of stages. The power consumption of a pipeline grows linearly with the number of bits, and offset requirements are reduced in the low resolution ADC stages when redundancy is applied. However, the ADC stages typically include linear residue amplifiers, which traditionally are implemented as operational amplifiers connected in a negative feedback configuration. The use of a closed feedback loop increases the power consumption.
Thus, there is a need for high speed ADCs that can achieve both high speed and high accuracy while simultaneously achieving low power consumption.